Shift and rotate circuit for a data processor



March 19, 1968 o. MUIR m 3,374,468

SHIFT AND HOTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 ll Sheets-Sheet 1 gwl3l2nlo9a I5I4I3I2II|098765432I0L D L INVENTOR 0. M0? .ZH'

ATTORNEY March 19, 196s D. MUIR m 3,374,468

SHIFT AND ROTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 11 Sheets-Sheet 2 Q Q I Q II Z//////// z I, g 5 Q v II 3 I, I 9 g I o I F: Q J1 CCD U Q LL March 19, 1968 D. MUIR m 3,374,468

SHIFT AND ROTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 11 Sheets-Sheet 5 FIGS/I II 30: OUTPUT INPUTS fi 13 30a T 3Q F/GJ'B 1| I2 F/G.3C 1| I2 I3 OUTPUT 0 0 o 1 0 o I 0 0 0 I 4 M o o r a o 1 0 I I 0 FIG/2 D. MUIR lll March 19, 1968 l1 Sheets-Sheet 6 Filed Aug. 10, 1965 mom March 19, 1968 D. MUIR m 3,374,468

SHIFT AND ROTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 ll Sheets-Sheet T March 19, 1968 0. MUIR m 3,374,463

SHIFT AND HOTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 ll Sheets-Sheet D. MUlR IH March 19, 1 968 l1 Sheets-Sheet 9 Filed Aug. 10, 1965 5 3 km 5 2m E m 9n. m j T 2 iii 6; Q5 m5 0 5 he m 1 b 1 mx K March 19, 1968 0. MUIR m 3,374,468

SHIFT AND ROTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 11 Sheet$-$heet 10 March 19, 1968 um m 3,374,468

SHIFT AND ROTATE CIRCUIT FOR A DATA PROCESSOR Filed Aug. 10, 1965 11 Sheets-Sheet 11 FIG.

United States Patent 3,374,468 SHIFT AND ROTATE CIRCUIT FOR A DATA PROCESSOR David Muir III, Minerva Park, Ohio, assignor to Bell Telephone Laboratories, Incorporated, New York, N.Y., a corporation of New York Continuation-impart of application Ser. No. 420,566, Dec. 23, 1964. This application Aug. 10, 1965, Ser. No. 478,536

16 Claims. (CI. 340-1725) ABSTRACT OF THE DISCLOSURE An arrangement which performs shift and rotate operations in either direction on data stored in a register. A plurality of mu1ti-element rotate circuits are connected in parallel between the input and output terminals of the register. Each rotate circuit is oriented to rotate the bits contained in the register stages by a predetermined different number of stages in the same one direction. Specified shift and rotate operations are performed in accordance with specified magnitudes and directions by controlling selected elements of the rotate circuits during additive sequential energization thereof to inhibit transmission of bits through the selected rotate elements.

This application is a continuation-in-part of my copending application Ser. No. 420,566, filed Dec. 23, 1964.

This invention relates to data processors and more particularly to shift and rotate circuits for use therein.

In many data processing systems it is necessary to shift and rotate data words. In conventional prior art data processors a word is first placed in one of the system registers. The word is then shifted or rotated, to the left or the right. Although the term shifting is used throughout this specification in its generic sense as including the rotate operation, a shift operation is distinct from a rotate operation. When the bits in the data word are shifted out of one of the ends of the register during a rotate operation they are reinserted at the other end of the register. When the word is to be shifted rather than rotated the bits shifted out of the register are not reinserted at the other end, and Os are written in the stages at this other end of the register. Since the data word may be shifted or rotated to the right or the left it is apparent that four distinct operations are possible. The magnitude of the shift in each case must be specified.

In prior art shift and rotate circuits it has generally been required to provide a first mechanism for rotating a data word to the right and a second mechanism for rotating a data word to the left. Shifts in either direction are accomplished by blocking the bits shifted out of one end of the register. The left rotation circuitry is usually identical to the right rotation circuitry except that the various connections are made in the opposite direction. Heretofore, it has been believed that a unidirectional rotate circuit could not be used to readily accomplish shifts and rotations in both directions.

It is a general object of this invention to provide shift and rotate capabilities in either direction by the use of unidirectional rotate circuitry.

In the illustrative embodiment of my invention the principles of the invention are applied to the type of shift and rotate circuit disclosed in the copending application of W. B. Cagle et al., Ser. No. 380,274, filed July 6, 1964, now US. Patent 3,350,692, issued Oct. 31, 1967. In the Cagle et al., system the bits in the register may be shifted 1, 4, 7 or 8 positions in any single step. Thus, for example, a gating path is provided from each stage to the stage four positions to the right and if all of these gating paths are operated together the entire data word is rotated four positions to the right in a single step. The other three sets of gating paths control the shifting of the data word 1, 7 and 8 positions to the right, respectively. In the Cagle et al. system instead of providing only one set of gates for shifting the data bits one position at a time, an additional three sets of gates are also provided. Although the circuitry is more complex, a shift or rotate operation can be executed very rapidly. For example, a shift of 19 positions to the right may be accomplished in only three steps by operating in succession the three sets of gates which control the shifting of bits 7, 8 and 4 positions, respectively.

Although the Cagle et al. system enables a data word to be shifted or rotated rapidly, the four sets of gates which control right shift and rotate operations are duplicated to control left shift and rotate operations. In accordance with the principles of my invention the duplicated gates in the left direction are not required since the right rotation circuitry may be used to accomplish all four types of shift operations. In the illustrative embodiment of my invention five sets of gates are provided, the gates in each set controlling respectively shifts to the right of l, 2, 4, 8 and 16 positions. Although in the illustrative embodiment of the invention shift operations may be executed by moving bits more than one position at a time, the invention may be most readily understood by considering the prior art type shift register in which bits are shifted only one position at a time.

If right rotation circuitry is provided right shifts may be easily accomplished. It is only necessary to block bits shifted out of the right end of the register from re-entry in the left end. Similarly, left rotation operations may be accomplished by first complementing the shift magnitude with respect to the number of register stages and then rotating the data word to the right. For example, if the data word is to be rotated seven positions to the left in a ZO-stage register, the left rotation operation may be accomplished by rotating the data word 13 positions to the right. However, it has been believed heretofore that certain prior art right rotation circuitry could not be used to accomplish left shifts. Even if the shift magnitude is complemented with respect to the number of stages in the register and the word is then rotated to the right, the bits which must eventually remain in the register are those which are shifted out of the right end of the register. Consequently these bits must not be blocked from reentry in the left end of the register. The bits which must be erased are those which never leave the register in the first place. For example, consider a left shift of four positions in a 6-stage register. Assume that the register initially contains a 6-bit data word represented by the following sequence: 6 5 4 3 2 1. If the (left) shift magnitude, 4, is complemented with respect to the number of stages, 6. the resulting shift magnitude is 2. If the bits are then rotated two positions to the right the register will contain the following sequence: 2 16 5 4 3. Now, if the original word in the register is to appear as if it was shifted four positions to the left the final word which should appear in the register is 2 l 0000, where a 0 represents the erasing of a bit. Thus it is seen that if the shift magnitude is first complemented with respect to the number of stages and the bits are then rotated to the right a number of stages equal to the complemented shift magnitude, the bits which must remain in the register are those which are shifted out of the right end and reinserted in the left end, and the bits which must be erased are those which are never shifted out of the right end of the register in the first place. Thus, unlike the case of right shifts, a simple blocking mechanism does not appear available to accomplish left shifts.

In accordance with the principles of my invention, left shifts are accomplished with the use of right rotation circuitry by erasing from the register those bits which do not leave the right end of the register. Advantageously, these bits may be erased during the shifting process, a bit being erased when it is determined that the bit will in no event leave the right end of the register by the time the shifting operation is terminated. In other words, Os may be written into some of the stages of the register even before the shifting operation is over if it is determined that the bits in these stages cannot possibly be shifted out of the register. This technique may be applied to conventional shift and rotate circuits in which the bits may be shifted only one position at a time and also to the improved shift and rotate circuit of Cagle et al. in which the shifting takes place in movements of more than one position at a time. In either case unidirectional rotate circuitry may be used to accomplish shift and rotate operations in both directions.

It is a feature of my invention to control the shifting and rotating of data words in either direction with the use of unidirectional rotating circuitry. with Us being Written automatically in certain ones of the register stages to accomplish an apparent shift in the direction opposite to that in which the unidirectional rotating circuitry is operative.

Further objects, features and advantages of the invention will become apparent upon consideration of the following detailed description in conjunction with the drawing in which:

FIG. 1 depicts the principles of operation of the shift and rotate circuit of the invention for a data processor in which data words are 16 bits in length;

FIG. 2 depicts the principles of operation of the shift and rotate circuit of the invention for a data processor in which data words are 20 bits in length;

FIG. 3A is a detailed schematic of an illustrative gate, shown symbolically in FIG. 3B, which may be used in the block diagram circuit of FIGS. 4l1, and FIG. 3C depicts the operation of the gate for various input conditions;

FIGS. 411 depict the illustrative embodiment of the invention, a shift and rotate circuit for use with a 20- stage register; and

FIG. 12 shows the arrangement of FIGS. 4ll.

Principles of operation for a 16-bit shift and rotate circuit (FIG. 1

In FIG. 1 a matrix array of nodes is shown, the array comprising 16 columns and 5 rows. Each node represents a stage of the register and all stages are represented at least 5 times. The nodes in each column represent the same register stage. Each node is identified by a number and a letter. For example, node 7D is in column 7 and row D and represents stage 7 of the register. Nodes 7A, 7B, 7C and 7E also represent stage 7 of the register. All nodes to the right of line LL have designations identical to respective nodes to the left of line LL and thus each stage is represented only once in each row.

A line, vertical or diagonal, between any two nodes represents a transmission path. The bit value at any node, i.e., in any stage, is transmitted either along the vertical path to the node in the next row in the same column, or along a diagonal path to a node in the next row but to the right. For example, considering the nodes in row C the bits in the register stages may remain unchanged or may be shifted to stages four positions to the right. The system, described in detail below, includes a single set of vertical gates each of which merely controls the rewriting of any bit in the register in the same stage. The system also includes four sets of diagonal" gates which control the shifting of the bits in steps of l, 2, 4 and 8 positions, respectively. To accomplish a right rotation four steps are required. During the first step either the set of vertical gates is operated, or the first set of diagonal gates, connecting adjacent stages, is operated. If the vertical gates are operated the data word in the register is unchanged. If the diagonal gates are operated the data word is shifted one position to the right. During this first step the transmission paths emanating from the row in row A of FIG. 1 are considered. If the vertical paths are taken the bits in the register remain unchanged since they are rewritten into the same stages of the register, i.e., the bits are transmitted to the same numbered nodes in row B. If the diagonal paths are taken the bits in the register are all shifted one position to the right.

During the second step either all of the vertical gates are operated or all of the diagonal gates which control the transfer of bits from each stage to the stage two positions to the right are operated. (In this connection it should be noted that the stage two positions to the right of stage 0 is stage 14, and the stage two positions to the right of stage 1 is stage 15.) If the vertical gates are operated the word in the register is unchanged. This is seen from an examination of FIG. 1 since the bit at any node in row B is transmitted down to the same numbered node in row C, i.e., the bit in any register stage is merely rewritten in the same stage. On the other hand, if in step 2 the diagonal paths are taken each bit in the register is rotated two positions to the right. Since, for example, node 108 is connected by a diagonal path to node 8C the bit in stage 10 of the register is shifted to stage 8 of the register. Similarly, the bit in stage 0 of the register is shifted to stage 14, etc.

in step 3 of the operation either all of the vertical gates are operated or all of the diagonal gates which connect respective stages to the stages four positions to the right are operated. If the vertical gates are operated the entire data word is merely rewritten in the register. If the diagonal gates are operated the data word is rotated four positions to the right. Again, either all of the vertical gates or a l of the gates in a set of diagonal gates are operated. Referring to FIG. 1 the hits at the nodes in row C are transmitted either directly down to the nodes in row D or to the right to the nodes in row D. Similar remarks apply to the fourth step in the operation during which the vertical gates are all once again operated or the gates in the fourth set of diagonal gates are all operated. In the former case the data word is merely rewritten in the register. In the latter case the data word is shifted eight positions to the right in a single step. It must be remembered that the actual operation performed is the writing of bits in the register stages rather than the shifting of bits from one set of nodes to another. This is depicted in FIG. 1 if it is borne in mind that the nodes in all five rows represent the stages of the same register. The node representation of FIG. I is helpful because it affords a clear visualization of the various overall shifting operations.

The illustrative embodiment of the invention is a 2D bit system, the switching scheme for which is depicted in FIG. 2. However before this latter relatively complex switching plan is analyzed the simpler plan of FIG. I must be understood. The implementation of a 16-bit system, based on the switching plan of FIG. 1 is analogous to the implementation of the '.Z(lbit system based on the switching scheme of FIG. 2. Consider first a right rotation operation in a 16-bit system. Suppose the shift magnitude specified is It positions. Since the choice of diagonal steps is limted to steps of l, 2, 4 and 8, to accomplish a shift of ll positions diagonal steps of l. 2 and 8 are required. Consider the bit initially in stage 7 for example. During the first step of the operation all of the diagonal paths between the nodes in row A and the nodes in row B are taken. Thus the bit at node 7A is transmitted to node 68, i.e.. the bit in stage 7 of the register is shifted to stage 6. During the second step of the operation the diagonal paths between the nodes in row B and the nodes in row C are taken rather than the vertical paths. The bit at node 613 is thus transmitted to node 4C, the bit in stage 6 is transferred via a respective diagonal gate to stage 4. During the third step of the operation all of the vertical paths between the nodes in row C and the nodes in row D are taken. Consequently the bit under consideration, now at node 4C, is transmitted down to node 4D. During this step all of the 16 vertical gates in the system are operated and the bit in stage 4 of the register is merely rewritten in the stage. During the fourth step of the operation all of the diagonal paths between the nodes in row D and the nodes in row E are taken rather than the vertical paths. Consequently the bit under consideration at node 4D, is transmitted to node 12E, i.e., the bit originally in stage 7 and now in stage 4 is transferred to stage 12 by the diagonal gate connecting stage 4 to stage 12. Thus after the four steps in the sequence the bit originally in stage 7 appears in stage 12, i.e., the bit has been rotated 11 positions to the right as required.

Right shifts are easily accomplished by blocking all of the diagonal gates represented by the diagonal transmission paths which cross line LL. It is to be recalled that during a right shift bits shifted out of the right end of the register must not be reinserted in the left end of the register. Thus during the first step in the operation if the vertical paths are taken none of the vertical gates are blocked. However if the diagonal paths are taken. i.e., all bits are shifted one position to the right, the gate which connects stage 0 to stage is blocked. When a gate is blocked a 0 is understood to be automatically written in the stage to which the gate transmits a bit. Thus when the transmission path between node 0A and node 158 is blocked the gate which connects stage 0 of the register to stage 15 of the register is controlled to write a 0 in stage 15 independent of the bit value initially in stage 0.

During the second step of a right shift operation if the vertical paths between the nodes in row B and the nodes in row C are taken none of the 16 vertical gates in the system are blocked. However if the diagonal paths are taken the bits which cross line L--L must be blocked. Thus the transmission paths between nodes 0B and 14C and nodes 1B and 15C must be blocked. The two gates which connect stages 0 and 1 of the register to respective stages 14 and 15 are controlled to automatically Write Us in stages 14 and 15 independent of the values of the bits in stages 0 and 1 at the termination of step 1.

A similar analysis of FIG. 1 shows that during the third step if the diagonal gates in the third set are operated four of these gates must be blocked since four diagonal paths between the nodes in row C and the nodes in row D cross line LL. The four diagonal gates connecting stages 0-3 to respective stages 12-15 are c0ntrolled to automatically write Us in stages 1215 independent of the values of the bits initially in stages 03 at the termination of the second step. Similarly, if the fourth set of diagonal gates are operated in the fourth step of the operation rather than the vertical gates, eight of these diagonal gates are blocked and Os are automatically written in stages 8-15 of the register independent of the values of the bits in stages 0-7, initially in the register at the termination of the third step. After the fourth step, either vertical or diagonal is taken, the bits which appear at the nodes in row E represent the shifted data word. i.e., the bits in the register are the same as the initial bits in the register except for their being shifted to the right by the required number of stages.

A rotation to the left is easily accomplished. The shift magnitude is merely complemented with respect to the number 16 and the complemented magnitude is used to control a right rotation operation. For example, to rotate the data word 7 positions to the left the data word is actually rotated 9 positions to the right. Thus the right rotation circuitry may be used to perform left rotations by merely complementing the shift magnitude with respect to the number 16 before using it as the steering word to control the actual (right) rotation.

The fourth operation which must be considered is a left shift. As described above it has heretofore been believed that certain prior art right rotation circuitry could not be used to accomplish left shifts. In accordance with an aspect of my invention however the right rotation circuitry may be used to accomplish left shifts with surprisingly few additional control functions. Although little additional circuitry is required the analysis may be quite complicated in any given system and for this reason the 16- bit case will be considered in detail at this time.

For performing left shifts with right rotation circuitry the proper steering Word may once again be obtained by first complementing the given shift magnitude with respect to 16. By then rotating the input data word to the right a number of positions equal to this complemented value, the input data word will be given the effect of being rotated the proper number of positions to the left. But during a shift operation 0's must be written at one of the ends of the output word. For right shifts US may be easily written at the nodes at the left end of the system merely by blocking the diagonal paths which cross the line LL. But a similar blocking technique for left shifts is difficult to envision because the bits which cross the line LL must remain in the system when the input data word is shifted to the left and those bits which do not cross line LL must be forced to be Os by the end of the operation. For example, consider an input data word which consists of 16 ls. Suppose the magnitude given for the left shift is 5. The final data word at the nodes in row E should be 1111111111100000. If the input data word is rotated 11 positions to the right the 11 least significant bits in the input word cross the line LL and appear in the 11 most significant positions in the final Word. It is only the five bits which do not cross the line LL which must be made Os during the course of their transmission through the system in order that the five least significant bits in the final word be all US. The changing of these five bits to Os appears diflicult because these five bits never cross the line LL and it is not obvious that a particular group of diagonal paths may be blocked such as in the case of a right shift.

The starting point in the analysis is the following principle, which may be deduced from the discussion immediately above: A left shift operation may be performed if the magnitude of the left shift called for is complemented with respect to 16 and then right transmission through the system is allowed only for those data bits which cross the line LL. If somewhere in the network US are substituted for the bits which do not cross LL, Os will appear, as required, at the rightmost nodes in row E.

The diagonal line DD is superimposed on the path ISA-0E, this latter path actually comprising four distinct transmission paths. All vertical paths passing through the line DD, and all vertical paths which terminate at a node along the line DD are dotted in FIG. 1. Thus the path 0D0E and the output path which goes downward from node 0B are dotted because they terminate at a node along line DD. The seven vertical paths lD-IE through 7D-7E are dotted because they cross the line DD. The two vertical paths 8C-8D and 8D-8E are dotted because they each terminate at node 8D which is along the line DD. The three vertical paths 9C-9D 11C-11D are dotted because they cross the line DD. The two vertical paths 12B-12C and 12C-12D are dotted because they each terminate at node 12C through which line DD passes. Vertical path 13B-13C is dotted because DD passes through it. The two vertical paths 14A-l4B and 14B14C are dotted because they each terminate at node 14B which lies along DD. Vertical path 15A15B and the vertical paths connected above node 15A are also dotted because they terminate at node 15A which lies along DD.

Once the dotted vertical paths are determined a left shift may be accomplished with the use of right rotation circuitry in a surprisingly simple manner. All that is required is that the left shift input magnitude be complemented with respect to 16 and the input data word then be rotated to the right a number of positions equal to the complemented value-with all of the dotted vertical paths being blocked, i.e., the nodes at the lower end of each of the paths having Os automatically written on. them when respective vertical steps are taken. By absolutely blocking the dotted vertical paths when a left shift op' eration is to be performed Os will automatically ap' pear in the required number of rightmost nodes in row D, i.e., tIs will automatically appear in the required numberof rightmost stages in the register. The blocking of the vertical paths which cross the diagonal D-D has the effect of allowing data bits to remain in the register only if they cross line LL. It might be observed that the four diagonal paths which lie along the line D-D could also be blocked without any adverse effect on the operation because the blocking of the dotted vertical paths ensures that no data bits ever arrive at nodes on the line D-D. A convenient use for the blocking of some of these diagonal paths will be described below.

In order to design a shift and rotate circuit for other than 16-bit data words it is necessary to clearly understand why blocking the dotted vertical paths in FIG. 1 insures that Os appear on the correct number of rightmost nodes in row E after the input data word is transmitted through the network. The selection of the vertical paths to be dotted is based on the fundamental principle given above. By blocking the vertical paths represented by the dotted lines it is guaranteed that Ds will be substituted for those bits in the original data word which do not cross the line LL by the time they reach the nodes in row E.

The vertical paths in FIG. 1 fall into three groups, the dotted paths along D-D, the vertical paths to the upper right of the dotted paths, and the vertical paths to the lower left of the dotted paths. The key to the vertical path scheme is to insure that a is substituted for any bit which cannot cross L-L during transmission through the network. Consider first the bits at the nodes at the upper right of the network. The bit at node 0A crosses LL if a diagonal step of one is taken. However if a vertical step is taken and the bit is transmitted to node 08 it may will subsequently cross L-L if a step of 2, 4 or 8 along a diagonal is taken. Consequently the vertical path connecting node 0A to node 08 should not be blocked. A 0 should not be substituted for the bit at node 0A even if a vertical step is taken because the bit may subsequently cross LL and should therefore remain in the system. Consider another node, for example, node 7C. By the time the bit appears at node 7C there has been a shift of at most three positions to the right. The bit at node 7C therefore has not yet crossed LL. The bit at node 7C may cross LL Whether the diagonal step is taken to node 3D or the vertical step is taken to node 7D. In either case the bit originally at node 7C may yet cross LL, if the next shift of 8 is along diagonal 7D15E or 3D-11E. Consequently the vertical path from node 7C should not be blocked, i.e., a 0 should not be substituted for the bit at node 7C, even if the vertical path 7C7D is taken because the bit may yet cross LL if a diagonal step of 8 is taken.

Consider now the nodes at the top of the dotted vertical paths beginning with the group of nodes 0D through 8D. By the time the original bits at the nodes in row A are transmitted to the nodes in row D a maximum shift of seven positions may have taken place. The only bits at the nodes in row D which may have already crossed LL are those at nodes D through 9D, the seven leftmost nodes in the row. In no way whatsoever can the hits at nodes 8D through 0D have already crossed LL. If these bits take the vertical paths downward from row D they will not have crossed LL by the time they appear at the output nodes 813 through 0E. In this event these bits will not have crossed L-L and they .should appear as 0s in the final word. For this reason if the diagonal step of 8 positions is not taken 0D should not be transmitted through the system and [is should be substituted for them. A blocked vertical path results in a 0 being written at the node at the bottom of the vertical path. Thus if the diagonal step of 8 positions is not taken, 0's are automatically written at nodes 8E through 0E, i.e., Os are automatically written in stages 8 through 0 of the register.

A steering word represents the actual shift magnitude for the right rotation. It comprises four bits, X1, X2, X4 and X8, each of these bits being a 1 only if the respective diagonal step is to be taken. Since the steering word represents the actual steps taken, its magnitude is the complement of the input magnitude with respect to 16 on left shifts. For example, if on a left shift the input magnitude is 9, the steering word is 0111.

Consider now the nodes in row C. The vertical paths downward from nodes 7C through 0C should not be blocked because even if the hits at these nodes take these vertical paths they may still cross LL if X8 is a 1. But the same is not true of nodes 12C through 8C. When the step of 4 is about to be considered the maximum shift through the network thus far has been 3. Consequently bits which have already crossed LL may appear at nodes 15C through 13C. But the hits at nodes 12C through 9C can in no way have already crossed LL. The bits at nodes 7C through 0C need not be controlled as explained above. This leaves only the bits at nodes 12C through SC. If the bits at these nodes take a vertical step from row C, thus appearing at nodes 12D through 8D, the bits cannot cross LL even if the diagonal step of 8 is next taken. The furthest that any one of these bits can get is to node 0E. Since the hits at nodes 12C through 8C have not yet crossed LL and can in no way cross LL if X4 is a 0 the vertical paths from nodes 12C through 8C are blocked. If X4 is a 0, Us are automatically written at nodes 12D through 8D.

Consider next the nodes in row B. No control need be exerted over the hits at nodes 11B through 013. The bits at these nodes may subsequently cross LL even if they take vertical steps from the nodes in row B to the nodes in row C. Even the bit at node 118 may cross LL after a vertical step to node 11C is taken if bits X4 and X8 are ls. Consequently no control need be exerted over the bits at nodes 118 through OB.

When the step of 2 positions is about to be considered the maximum shift that may have already been taken is 1. Consequently, the bit at node 15B may already have crossed LL, the bit having come from node 0A. But the bits at nodes 14B through 12B cannot yet have crossed LL and if these bits take vertical paths at row B there is no chance that they will subsequently cross LL even if X4 and X8 are ls. Even the bit at node 128 cannot cross LL if it is transmitted vertically down to node 12C. If X4 and X8 are both ls this bit may progress no further than to node 0E. Since the three bits at nodes 148 through 12B cannot cross LL if X2 is a 0 the three respective paths are blocked. By blocking these paths and automatically writing Os at nodes 14C through 12C these bits will appear as (TS in the final data word.

Consider next the nodes in row A. The bits at nodes 13A through 0A may cross LL even if X1 is a 0. For example, the bit at node 13A, even if transmitted vertically to node 138, may still cross LL if X2, X4 and X8 are all is. For this reason no control need be exerted over the bits at nodes 13A through 0A. But nodes 15A and 14A must be controlled. If X1 is a O the two most significant bits in the system would attempt to be transmitted to nodes 158 and 148. These bits then can in no way cross LL even if X2, X4, and X8 are all ls. At most the bit at node 14B can progress to node 0E. Consequently the two vertical paths 15A15B and 14A 14B are blocked during the left shift operation. Thus if the complemented shift magnitude word contains a 0 for the X1 bit Ds must be automatically written at nodes 158 and 14B, i.e., lls must be automatically written in stages 15 and 14.

It will be noted that the vertical line to the top of node 15A is also dotted. The maximum right rotation magnitude which may be specified is 15. Consequently the bit a node 15A can never cross LL since it can progress to at most node E. The minimum magnitude which may be specified on a left shift is 1. If a left shift of 1 is specifled the data word is rotated to the right positions. By always writing a t) at node 15A, a i) will then appear at node 0E. This is required since it is obvious that on any left shift, other than the trivial case of a left shift of zero places, a 0 must appear in at least the least significant position of the final data word. For this reason the output path downward from node 015 is blocked for left shift operations. Some further implications of these last mentioned two dotted paths will be described below.

Thus by blocking all of the dotted vertical paths it is guaranteed that 0's will be substituted for any bits which appear at the nodes at the top of these paths which have no chance of crossing L L. The nodes in the group at the upper right of the network need not be controlled since the hits at these nodes may cross LL even if vertical steps from these nodes are taken. The only nodes that remain to be considered are those to the lower left of the dotted vertical paths, namely nodes 15E through 1E, 15D through 9D, 15C through 13C, and 15B. The bits at these nodes also need not be controlled. If a 0 appears at one of these nodes it need not be controlled since to block vertical transmission would also result in a 0 being transmitted through the network. And if the bits at these nodes are ls they must have already crossed LL and consequently should remain in the network. The bit at node 150, for example, cannot have come from node 15A since the bit at node 15A is always a 0 on left shifts. If the bit at node 15C is a 1 it must have come from node 0A after a diagonal shift of 1 and a vertical step of 2, from node 1A after a vertical step of l and a diagonal shift of 2, or from node 2A after diagonal shifts of both 1 and 2. In any case the bit at node 15C has already crossed LL and need not be controlled at node 15C. Similarly, any ls appearing at the other nodes must have already crossed LL and, since they should remain in the system, the vertical paths from these nodes should not be blocked.

(It should be noted that in the particular example of FIG. 1 shifts and rotations of 16 are not permitted since the maximum value of the steering word is 15. Also, if a circuit is designed for a 16-bit system based on FIG. 1 arrangements must be made for the trivial case in which a shift magnitude of 0 is specified on a left shift or rotation operation. The complement of 0 with respect to 16 is 16 and the network is capable of a maximum rotation of only 15. Provision must be made for these cases if a 16-bit circuit is constructed. The additional circuitry required will be apparent to those skilled in the art, especially after the more complicated case of a 20-bit system is considered below. The 16-bit network plan is being described primarily because without this foundation an understanding of the 20-bit system scheme is exceedingly difficult.)

The 16-bit case is a relatively simple one. The right rotation circuitry is used and no paths are blocked on rotations to both the right and the left, with the given shift magnitude being complemented in the latter case before the left rotate operation is actually effected by means of a right rotate operation. A right shift is accomplished by controlling an ordinary right rotate operation but with the diagonal paths crossing LL being blocked, i.e., Gs being Written at the nodes at the ends of these paths whenever the steering control word indicates that these paths should be taken. Finally, a left shift may be accomplished by first complementing the given shift magnitude and then performing a right rotate operation with the dotted vertical paths being blocked. By blocking the dotted vertical paths unconditionally in the case of a left shift it is guaranteed that the only is in the original data word which are transmitted all the way through the network to the nodes in row E are those which cross L-L.

What the preceding analysis has shown is that in FIG. 1 (and any like network where the number of bits in the data word is an integer power of two) there conveniently exist three non-overlapping sets of nodes and paths as follows: the sets of nodes and paths typical of those in the upper right portion of FIG. 1 which includes all those nodes and paths which may be used by data bits prior to crossing line LL; the set of nodes and paths typical of those in the lower left portion of FIG. 1 which includes all of those nodes and paths which may be used after data bits have crossed line LL; and the set of nodes and paths typical of those on the diagonal in FIG. 1 which belong to neither of the two prior mentioned sets and which are in no case needed by any data bit prior to crossing line LL nor any data bit which has crossed line LL. This latter set in FIG. 1 consists of all the dotted paths, all of the nodes with dotted paths above and below them, and the diagonal paths along line DD from node 15A to node 0E. Although all of the dotted vertical paths were assumed to be blocked in the preceding discussion, a sufficient technique for using the network of FIG. 1 to accomplish the left shift operation is to block a subset of the dotted vertical paths along line DD and the diagonal paths along line DD, such subset being chosen so that each input data bit is forced to cross line LL if it is to proceed through the entire network without being blocked. It will be recalled that FIG. 1 is merely a convenient representation of the shifting operation as it occurs in the register stages. The signals at the nodes of row A may be thought of as the condition of the register at the beginning of the shifting operation and the signals at the nodes of row E may be thought of as the condition of the register at the end of the shifting operation. Blocking the vertical path to the top of node 15A would, then, imply that register stage 15 is forced to be a 0 prior to the start of the shifting operation. Similarly, blocking the path leading downward from node 0E would imply the forcing of register stage 0 to be a 0 after the shifting operation is finished. In order to avoid such complications, one convenient subset of paths to block in FIG. 1 to accomplish the left shift operation would be to block all dotted vertical paths which intersect a line parallel to and just above line DD except the vertical path to the top of node 15A. Then, additionally, block the two paths downward from node 15A. The blocked paths then would consist of those between the pairs of nodes 15A15B, ISA-14B, l4A-l4B, l3B-l3C, l2Bl2C, 1lC1ID, 10C- 10D, 9C9D, 8C8D, 7D-7E, 6D-6E, SD-SE, 4D4E, 3D-3E, 2D-2E, lD-IE, and OD-OE. It will be noted that this subset fulfills the requirement that each data bit is forced to cross line L-L if it is to proceed through the network without being blocked, i.e., if it is to appear in the register after the shifting operation is complete. Other choices of the subset of paths to block exist.

In the 16-bit case a subset of paths are blocked unconditionally. These paths are never operative when a left shift operation is being performed. In fact, in any system where the number of bits is a power of 2 and the shift magnitude word is of the form (X32) (X16) (X8) (X4) (X2) (X1) a network similar to that shown in FIG. 1 may be drawn with little difficulty. The line DD is drawn straight through the two nodes in the upper left and lower right corners. All vertical paths passing through DD and all vertical paths which terminate (either at the top or bottom) at a node fal ing on line DD are dotted. A suitable number of vertical or diagonal paths are unconditionally blocked on all left shifts and no additional control need be exerted to insure that the only ls which are transmitted through the system are those which cross LL, i.e., those which should not be replaced by US at the right end of the final word. The more diflicult situation is that in which the number of bits in a data word is not a power of 2. In such a case some of the paths may not be unconditionally blocked. In certain cases these paths must remain open, i.e., they must transmit ls down them, under special circumstances. For an appreciation of the more complicated situation attention is now directed to FIG. 2 which shows the network for a 20-bit system.

Principles of operation for a 20-bit shift and rotate circuit (FIG. 2)

It is assumed that the 20-bit shift and rotate network of FIG. 2 shall be required to accept commands to shift or rotate either left or right with any specified input shift magnitude from 0 through 20 places. Input shift magnitudes of greater than 20 positions are assumed to he of no interest and not allowed as a valid input command.

A five-bit shift magnitude word is required to specify one of the numbers 0-20. The steering Word is thus represented as (X16) (X8) (X4) (X2) (X1). The steering word, the word which actually controls the transfer of bits in the stages of the register, is identical to the input shift magnitude if the shift or rotate operation is to the right, and is the complement of the input shift magnitude with respect to the number 20 if the shift or rotate operation is to the left. An additional group of vertical and diagonal transmission paths are used to control transmission from the nodes in row E to the nodes in row F. Shifts are accomplished in steps of l, 2, 4, 8 and 16. FIG. 2 is to be interpreted in the same manner as FIG. 1. Transmission paths are provided for transmitting bits either vertically or diagonally to the right, these paths being the only ones required to control all four possible operations.

The operation of a 20 -bit system when a 20-bit data word is to be rotated to the right is straightforward. For example. to rotate the word 19 positions to the right the input shift magnitude word is used as the steering word and is 10011. The diagonal gates wh ch are operated are those coming from the nodes in rows A, B and E. The vertical paths which are used are those originating at the nodes in rows C and D. The final rotated data word appears at nodes 19F through 0F. To rotate to the left the shift magnitude is complemented with respect to 20 and the data word is then rotated to the right a number of positions equal to the complemented value. For example, to rotate one position to the left the shift magnitude 00001 is first complemented with respect to 20. The resulting steering word 100|1 (decimal 19) is then used to control the right rotation. To shift to the right it is only necessary to block all diagonal paths crossing LL. By then controlling the automatic writing of Us at any node at which a diagonal path crossing LL terminates, it is irsured that Os appear in the proper number of the leftmost nodes in row F, i.e., Os appear in the proper number of the leftmost stages in the register. To control a left shift in a 20-bit system using right rotation circuitry is not as simple however as in the 16-bit case. The reason for this is that the vertical paths crossing the line DD cannot in all cases be unconditionally blocked. Further analysis is required to determine which vertical paths must be blocked to accomplish a left shift.

In the 16-bit network of FIG. 1 there conveniently existed a set of dotted vertical paths which were never needed by data bits which had already crossed line LL nor by data bits which would cross LL at later stages of the network. This set of dotted paths was large enough that a subset of them could be chosen in such a manner that blocking this chosen subset for left shift operations would force data bits to cross line L-L were they to gain transmission through the network. However, in the network of FIG. 2, which is typical of the situation where the number of bits in the data word is not an integer power of two, the set of paths which are never needed by data bits which have already crossed line LL nor by data bits which will cross L-L at later stages of the network consists of so few paths that a subset of them cannot be chosen and blocked unconditionally for left shift operations thereby forcing data bits to cross line LL if they are to gain transmission to the output termina s of the network. In fact. in FIG. 2, there exist paths such as 13D-13E which may be required by bits which have crossed LL or by bits which will later cross LL.

A starting point in constructing the network for any system in which the number of data bits is not an i ltegcr power of two is to draw the line DD just below the diagonal path from the extreme node at the upper left (i.e., just below the line from 1A to SF in FIG. 2). All of the vertical paths crossing DD are then made dotted. The set of nodes and paths to the lower left of the set of dotted paths includes all of the nodes and paths required by data bits which have already crossed line LL. Thus blocking conditions imposed on the dotted paths can in no way affect any data bits which have crossed LL. The technique for using the network of FIG. 2 to accompish left shift operations will be explained in detail below but it is, in essence, to block the set of dotted vertical paths unless a data bit using a particular dotted path is being steered at subsequent stages of the network to cross line LL.

There are 20 dotted vertical paths in FIG. 2. one for each column. It will be recalerl that in FIG. 1 all of the vertical paths in the circuit network fall into three distinct groups, the dotted vertical paths, those at the upper right of the drawing, and those at the lower left. In FIG. 1 the vertical paths at the upper right are not controlled on left shifts because even if these paths are taken the hits at the respective nodes can subsequently cross l.-L. (The basic ruYe for controlling a left shift is still the same: The input shift magnitude is complemented with respect to the number of bits in a data word and a right rotation is then controlled. with the only ls in the original word which are allowed to be transmitted to the output nodes being those which cross LL sometime during their transmission through the network.) In the 20-bit system of FIG. 2 the same remarks apply to the nodes and vertical paths at the upper right of the drawing. Even if the bits at these nodes take the respective vertical paths they may still cross L-L later on and for this reason the vertical paths at the upper right should not be blocked. In FIG. 1 all of the dotted vertical paths are unconditionally blocked. No blocking of the vertical paths at the lower left is desired because ls at the nodes at the top of these paths must have already crossed LL. But in FIG. 2 the dotted vertical palhs are not all unconditionally blocked and it is possible for 1s in the original data word to be transmitted down these dotted paths under certain circumstances to the nodes at the lower left of the drawing. For these reasons consideration must also be given to the vertical paths at the lower left of the drawing, although as will be seen below the control used for the dotted vertical paths is such that no control is required for the vertical paths at the lower left of the drawing.

It must first be appreciated why all of the dotted vertical paths may not be unconditionally blocked. Consider path 12D-I2E which crosses D-D. When the bits in the input word appear at the nodes in row D a step of 8 is about to be considered. The maximum possible shift taken in the first three steps is 7 (if X1, X2 and X4 are all ls). The bit at node 12D, i.e., the bit in stage 12 of the register after the third of the five steps in the sequence has been taken, can in no way have already crossed LL. The bit at node 12D may have come only from one of the nodes 12A through 19A. Following the pattern set down in FIG. 1 path 12D12E should be unconditionally blocked it X8 is a 0. In FIG. 1 the dotted vertical paths are blocked because, were they to be taken, the bits at the nodes at the tops of the paths could in no way subsequently cross LL by the time they appear at the final row of nodes. But the bit at node 12D in FIG. 2 can cross L-L even if X8 is a 0. If X8 is a t) the bit at node 12D is transmitted to node 12E. As long as X16 is a 1, the bit at node 12E will cross LL and end up at node 16F. Consequently vertical path 12D-12E cannot be unconditionally blocked because the bit at node 12D may yet cross L-L even if vertical path 12D-12E is taken. It will be noted however that the bit at node 12D can cross LL even if the vertical path is taken only if X16 is a 1. Consequently vertical path 12D-12E should be blocked conditionally. i.e.. a should be automatically written at node 12E if X8 is a 0 unless X16 is a 1. If X16 is a 1 vertical path 12D-12E need not be blocked because it is guaranteed that the bit at node 12D will subsequently cross L-L.

It is necessary to derive a suitable transmission function for each of the dotted vertical paths in FIG. 2. The transmission function for each path essentially states the following: On a left shift the path is to be blocked unless it is guaranteed that the bit at the node at the top of the path will subsequently cross IEL. The method now to be shown may be used for deriving the transmission functions of the vertical paths crossing the line D-D in other systems. Each transmission function is a Boolean expression. The total expression is a 1 if the respective vertical path is to be operative. It is a 0 if the respective vertical path is to be blocked and a 0 is to be automatically written at the node at which the path terminates. In the transmission functions to be derived the expression (HL) represents an input command to perform a left shift operation. BL is a 1 if a left shift is to be performed. It is a 0 if one of the other three possible operations is to be carried out.

The five nodes 4E through 0B are first considered. The input bits appear at these nodes when the step of 16 positions is about to be taken. Up to this point the maximum shift which may have taken place is (8+4+2+1). Bits at nodes 19E through 515 may have already crossed LL. But the bits at nodes 4E through 0E may in no case have already crossed LL, since node 4E is 16 positions to the right of line LL and nodes 313 through 0E are even further away. If the diagonal step of 16 is not taken from these five nodes the bits at these nodes will not have crossed LL by the time they appear at the nodes in row F. For this reason the vertical paths from nodes 4E through 0E must be unconditionally blocked on left shifts. The transmission function for the five vertical paths 4E-4F through 0E0F is Kilt (it). (The term X16 represents the most significant bit in the steering word after it has been formed from the complement of the input shift magnitude. In other Words, X16 is a 1 if the diagonal paths from nodes E are to be taken.) The transmission function (W) m) for the five vertical paths 4E-4F through 0E0F depicts the operation of the paths in all cases. In the three cases other than left shifts HL is a 0 and ET, is a 1, thus making the path transmission only a function of the steering term m. If X16 is a 0, W is a 1 and the transmission function is a 1. The vertical paths may be used as required. If X16 is a 1, m is a 0 and the vertical paths are blocked. Even though a left shift operation is not being performed the vertical paths may be blocked by the steering term because they are not required. (Although the blocking of a vertical path has been described above as controlling the automatic writin g of a 0 at the node at the bottom of the path, a 0 is automatically written at the node only if a 1 does not come along the diagonal path terminating at the same node. Thus when X16 is a 1 although the five vertical paths may be blocked, ls may appear at nodes 4F through 0F if ls originally appear at nodes 0E and 16E through 198.) If, on the other hand, HL is a 1 indicating that a left shift operation is being performed HT is a 0,

14 and the five vertical paths are blocked no matter what the value of X16. This is the desired operation. If X16 is a 0 the vertical paths would normally transmit ls but instead are blocked as required. The blocking of vertical paths 4E4F through (IE-0F on left shifts is unconditional as seen from the transmission function (TIT) 3% Consider neXt nodes 12D through 5D in row D. When a step of 8 is about to be taken the maximum shift which can thus far have taken place is 7 (4+2+1). Bits which have already crossed LL may appear at nodes 19D through 13D but the bits at node 121) and the bits at nodes to the right of 12D can in no way have already crossed LL. If X8 is a 0 and the eight vertical paths 12D-12E through 5D5E are taken it is still possible for the bits originally at nodes 12D through 5D to cross LL. Even if these vertical paths are taken and the bits are transmitted to nodes 12E through 5E the eight bits may still cross L-L in the last step if X16 is a 1. Consequently while the eight vertical paths should be blocked on left shifts if X8 is a 0, the blocking is conditional. The paths must not be blocked if X16 is a 1. If X16 is a 1 the eight vertical paths may be used even through the bits which are transmitted down them have not already crossed L-L because it is guaranteed that the bits will subsequently cross LL in the last step.

The transmission funclion for the eight verti:al paths 12DI2E through 5D5E is (T\ S) (TIT) +Xl6. On the three operations other than left shifts BL is a 0, TIT is a 1 and thus the bracketed expression is also a 1. For these three operations there is no need to block the vertical paths other than as a function of the steering term, X8. If X8 is a 0, :K 8 is a 1 and the transmission function is a 1; the paths are indeed not blocked. If X8 is a 1, W3 is a 0, the transmission function is a 0 and transmission through the vertical paths is denied by the steering term. If a left shift operation is being performed, on the other hand, HL is a l and fit is a t). In this case the transmission function reduces to (ft '5) [X16]. If X16 is a 0 the transmission function becomes a 0. This is the desired action; on left shifts the eight vertical paths 12D-12E through SD-SE should be blocked if X16 is a 0. On the other hand, if X16 is a 1 the transmission function reduces to the steering term E. Thus the vertical paths are not blocked. This is the required action since these eight vertical paths are to be unblocked and allow vertical trans mission if X16 is a 1 even on left shifts.

Consider next the bits at nodes 15C through 13C. (Node 16C which is also at the top of a dotted vertical path between rows C and D will be considered afterward.) When a step of 4 is about to be taken the bits at nodes 15C through 13C cannot possibly have already crossed LL. The three vertical paths l5C-15D through 13C-13D should be blocked on left shifts unless it is guaranteed that the bits at nodes 15C through 13C will subsequently cross LL. Regardless of the value of X8 the three bits which are transmitted down to nodes 15D through 13D can still cross LL if X16 is a 1. If X8:1 a shift of 8 is taken between rows D and E but X16 must also be a 1 for these bits to cross LL (X8 and X16 would actually never both be ls because this would imply a steering word whose value is greater than 20). Consequently the three bits at nodes 15C through 13C are guaranteed to subsequently cross LL even if the dotted vertical paths are taken if and only if X16 is a 1. Thus these three vertical paths must be conditionally blocked in the same manner as the eight vertical paths 12D-12E through 5D-5E. The transmission function for these three paths is identical to the transmission function previously considered except that the steering term (Kg) is replaced by the term (m). The transmission function for the three vertical paths 15C-15D through 13C-13D is thus (RI) [H+X16l.

It is also impossible for the bit at node 16C to have already crossed LL when the step of 4 is about to be it? taken since the maximum shift thus far may be at most 3 (2+1). But path 16C16D is in a different category than paths 15C15D through 13C-13D. If the vertical path l6C-l6D is taken it is impossible for the bit at node 16C to subsequently cross LL even if X16 is a 1. Since the input shift magnitude and the steering word which is the complement with respect to 20 of this magnitude must be 20 or less, XS must be a 0 if X16 is a 1 and the bit at node 16C, if X4:O, can progress no further than to node 0E. Consequently the bit at node 16C may in no case cross LL if the vertical path 16C-16D is taken. Thus path 16C16D must be unconditionally blocked. The transmission function for this path is (filtfi). On all operations other than left shift, (Yl l is a 1. 1f steering function X4 is a 0, fi is a 1, the transmission function is a 1 and vertical path 16C16D may be taken as required If X4 is a 1 the transmisission function is a 0 as required for proper steering of bits through the network. If, on the other hand, HL is a l as it is for left shifts,

(TIT) is a 0, the transmission function is a 0 and the verif tical path is unconditionally blocked.

When a step of two positions is about to be taken the bits in the original word may have already been shifted a maximum of one position. Thus, the bits at nodes 183 and 178 in no way may have already crossed LL. Suppose these bits take the respective vertical paths to nodes 18C and 17C. For the bit transmitted to node 17C to cross LL it must yet be shifted 18 positions to the right. The bit at node 18C must yet be shifted 19 positions to the right. The only steps remaining are those of 4, 8 and 16 positions. Steps of 8 and 16 positions are both not allowed. The only combination of steps guaranteeing that both bits cross LL is 4 and 16. Consequently, paths 18B-18C and 17B17C should be blocked on all left shifts unless X4 and X16 are both ls. The transmission function for these two paths is (T2) [TTIT-l-(XlfiMX-Ul. This transmission function describes the action of the two paths during all four types of operation. On the three operations other than left shift (TIT l) is a 1. The vertical paths transmit data bits if X2 is a 0. This is the required action since the two paths should function in the normal manner whenever a vertical step is required between nodes 188 and 18C and nodes 178 and 17C on all operations other than left shift. If X2 is a 1 the two paths do not transmit data bits since the diagonal paths are taken rather than the vertical paths from nodes 188 and 1713. On left shifts m is a 0. If X2 is a 0, X? is a 1 but the transmission function is a 1 only if both X4 and X16 are ls. Thus, the vertical paths are blocked on all left shifts unless it is guaranteed that is transmitted down these paths will subsequently cross LL.

The last dotted vertical path crossing D-D to be considered is 19A19B. The transmission function for this path is the same as the one just derived for paths 18B-18C and 17B17C. If a 1 at node 19A is transmitted vertically to node 19B it can cross LL only if it is subsequently shifted 20 positions to the right. Consequently, the path is blocked on all left shifts unless both X4 and X16 are ls. It should be noted that if X4 and X16 are both 1s and the operation being performed is a left shift, the original uncomplernented shift magnitude must have been zero. Path 19A-19B will thus be blocked on all left shifts unless the input data word is not to be shifted at all. This is the required action because if the data word is shifted at all to the left, the bit at node 19A, the leftmost bit in the original data word, must be erased from the system.

The 20 transmission functions just derived for the 20 dotted vertical paths define the action of these paths on all four types of operation. The vertical paths to the upper right of these paths need not be controlled other than by the steering functions because the bits at the nodes at the tops of these paths may subsequently cross LL even if they take vertical steps. Thus no special control is required of these vertical paths when a left shift is being performed. No special control is ever required for a vertical path when one of the other three types of operation is being performed. Consequently, the transmission function for each of these paths is merely of the form (X7). Each of these paths transmits a bit down through it only if its controlling bit in the steering word is a 1). 1f the controlling bit is a l and the diagonal paths are to be taken, the transmission functions for the vertical paths are Os.

The last group of vertical paths to be considered are those at the lower left of the drawing. In P16. 1 the transmission functions for these paths are merely of the form (Xi). Even on left shifts transmissions should be granted if Xi is a 0 because any ls which appear at the nodes at the tops of these paths must have already crossed L--L. The same is not true, however, if the vertical paths at the lower left of FIG. 2. Because some of the dotted vertical paths may not be blocked on left shifts ls may be transmitted down these paths to the nodes at the lower left of the drawing even if they have not yet crossed LL. But it is to be recalled that is are so transmitted down the vertical paths only if it is guaranteed that they will subsequently cross LL. Consequently, it is not necessary to provide additional blocking for any of the vertical paths at the lower left of the drawing. The transmission functions for these paths is again of the form (ii).

The transmission functions for the diagonal paths must yet be derived. Almost all of the diagonal paths have transmission functions of the form (Xi). The diagonal paths are taken whenever the respective controlling bits in the shift magnitude word are ls. The diagonal paths whose transmission functions are not of the simple form (Xi) are those which cross LL. It will be recalled that on right shifts these paths must be blocked. The transmission functions for the diagonal paths crossing LL are thus of the form (Xiflfifi). HR is a 1 only when the operation performed is a right shift. When a right shift operation is performed the diagonal paths crossing l.--L are blocked since their transmission functions are (Ts. When one of the other three types of operation is being performed HR is a l) and the transmission functions of the diagonal paths crossing L-L are reduced to the form (Xi) since these diagonal paths are controlled in the same manner as are the other diagonal paths in the network.

The analysis of FIG. 2 has been given in order that the method of derivation of the transmission functions for all types of paths be understood even when they must be derived for a system in which the number of bits in a data word is not a power of two. PIGS. 4-ll show an illustrative circuit implementation for a 20-bit system based on the network of FIG. 2.

20'2": shift and rotate circuit (FIGS. 4-11) The gates in the shift and rotate circuit are shown only in block diagram form. Before proceeding to an analysis of the shift and rotate circuit it is necessary to consider the particular gate circuit used. The basic gate circuit is shown in FIG. 3A, FIG. 3B showing the symbolic notation for the gate used throughout the detailed drawing. FIG. 3C is a table indicating the output of a three-input gate for the eight combinations of input signal levels.

The operation of the gate may be succinctly described as follows: The output is low (0) only if all inputs are high (1). Conversely, the output is high if at least one input is low. Throughout the illustrative embodiment of the invention, low level (ground) signals represent 0's, and high level signals represent ls. Referring to FIG. 3A, if all inputs are high all of the input diodes are reverse biased. Consequently, current flows from source 300 through resistor 301, diode 303 and the base-emitter junction of transistor 3Q]. The transistor conducts and the output is short circuited through the transistor to ground.

Thus. if all inputs are high, the output is low. However, if at least one input is low, current from source 300 flows through the respective input diode to the low level input source. Current does not flow through diode 303, and transistor 30! remains nonconducting. The collector of this transistor, the output of the gate. is thus high, equal in magnitude to the potential of source 302. All that is required is for one of the inputs to be low for the output to be high.

FIG. 3C illustrates the operation of the gate when three inputs are provided. The output of the gate is a 1 if at least one of the inputs is a 0. The output is low only if all inputs are high. If a particular gate has only one input it functions as an inverter. If the input is low the output is high, and if the input is high the output is low.

The particular gate employed in the illustrative embodiment of the invention is advantageous for the following reason. The outputs of two gates may be tied together and the combined output will be low if either of the individual outputs is low. Referring to FIG. 3A it will be noted that even though transistor 3Q! may not conduct, the output may still be low if the output terminal is shorted to ground through the transistor in some other gate whose output terminal is connected to ground through the respective transistor. In the system described below an input bus to each register stage is fed by a variety of gates, a vertical gate from the same stage and a group of diagonal gates from stages to the left. Only one of these gates is to function during any step because either all of the diagonal gates in one of five groups or all of the vertical gates operate. By controlling the transistor in the unoperated gates to remain off the potential on each input bus will be controlled solely by the operation of the selected gate. If the transistor in this gate does not conduct the potential of the input bus will be high. If the transistor does conduct however the potential of the bus will be low. Consequently the potential (n each input bus may be controlled in accordance with the state of only one of the register stages. The unoperated (or blocked) gates always supply high potentials for the input busses. It is the selected gate which actually controls the potential of the bus depending on whether or not the transistor in this gate conducts.

The detailed electronic 20-bit shift and rotate circuit, based on the network of FIG. 2, is shown in FIGS. 4-11, the arrangement of the figures being shown in FIG. 12. The 20-stage register comprising STO through ST19 is shown at the top of FIGS. 6-8. Directly beneath the register stages is the set of 20 vertical gates 0V-19V. FIGS. 68 also contain the three sets of diagonal gates All-A19, B0-Bl9 and (ti-C19, these three sets of diagonal gates controlling respectively shifts of l, 2 and 4 positions to the right. FIGS. 9-ll contain the last two sets of diagonal gates D0D19 and E0-E19, which control respectively shifts to the right of 8 and 16 positions. FIGS. 4 and 5 contain the control circuitry which governs the operations of the six sets of gates on FIGS. 6-11. The control circuitry determines which gates should operate at any instant to control the proper operation on the data Word initially in the register. Additional circuitry, not shown, is used to first write a word in the register. The details of this circuitry are not necessary for an understanding of my invention.

Each stage is connected to an input bus and an output bus. If the stage represents a 0 the output bus is low in potential and if the stage represents a 1 the output bus is high in potential. To write a bit in a register stage the opposite potentials are required. Thus to write a O in a stage the input bus must be high in potential and to write a l the input bus must be low in potential. At the top of each stage there is a trigger lead connected to conductor 505. Once a bit appears in a register stage the stage is unaffected by the potential on the input bus. When a pulse appears on the trigger input however a new hit is written into the stage depending on the potential of the input bus. Once the trigger pulse terminates the potential on the input bus once again has no etiect on the stage. The register stages STO through ST19 have sufficient internal delays in responding to the trigger that the output busses do not change value until after the trigger terminates.

There are six gates which terminate on each input bus. For example. consider stage 10. Gate 10V controls the potential on the input bus in accordance with the potential on the output bus. In other words gate 10V is the vertical gate which merely controls the rewriting of the bit in stage 19 ot' the register. Diagonal gate All is the gate in the first set which transmits the bit on the output bus of stage 11 to the input bus of stage 10 when a step of one position to the right is taken. Gate B12 is the diagonal gate in the second set which transmits a bit from the output bus of stage 12 to the input bus of stage 10 when the gates in the second set are operated. The gates in the third, fourth and fifth sets which are connected to the input bus of stage 10 are C14, D18 and E6. These three gates are the ones which connect the output busses of the stages 4, 8 and 16 positions to the left of stage 10 to the input has of stage 10.

In the absence of any control signals none of the gates on FIGS. 6ll is operated, i.e., the output potentials of all gates are high. Thus since the output potentials of the six gates connected to each input bus are high the input bus is also high in potential. In each step of an operation the 20 vertical gates or the 20 gates in any diagonal set are operated. Since only one gate connected to any input has may be operated it is seen that the potential on the bus depends solely on the operation of this gate. The output potentials of the other five gates connected to the bus are high. If the gate operated in the step produces a high potential at its output the input bus remains high in potential and when the trigger pulse appears on conductor 505 a G is written in the stage. If the output of the operated gate is low in potential the potential of the input has is low and when the trigger pulse appears on conductor 565 a l is written into the stage.

The control signals are derived on FIGS. 4 and 5. The commands transmitted to the control circuit are derived electronically but. since the derivation of these signals is not necessary for an understanding of the invention, the origination of the command signals is shown symbolieally only at the left of FIG. 4. Conductors HR, HL, QR and QL are all normally low in potential. When any operation is to be performed only one of these conductors goes high in potential. The conductor which goes high is HR on a right shift. HL on a left shift, QR on a right rotate and QL on a left rotate operation. At the same time that a positive potential is applied to one of these four conductors to specify the type of operation to be performed, control potentials are applied to the five magnitude leads A1, A2. A4, A8 and A16. The potentials on these conductors represent five bits in a binary code which specifies the magnitude of the desired shift. This magnitude is the uncomplemented value and is the actual magnitude of the shift operation to be executed. The primary purpose of the circuitry on FIG. 4 is to derive the steering word which actually controls the shifting of the bits in the register.

The steering bits which control the shifting appear on conductors X16, X8, X4, X2 and X1. Leads T6, E, R1

' E and m carry the complements of the bits on the respective steering leads, the complemented bit values also being required to control the shifting. The five leads X16, X8, X4, X2 and X1 are at potentials identical to those on respective leads A16. A8, A4, A2 and A1 if the direction of the shift is to the right. However if a left shift or a left rotation operation is to be performed the steering word on leads X16X1 is the complement of the shift magnitude on leads AlfiAl, with respect to the decimal number 20. FIG. 4 includes the circuitry for 

